Low power architecture of logic gates using adiabatic techniques

The growing significance of portable systems to limit power consumption in ultra-large-scale-integration chips very high density, has recently led rapid and inventive progresses low-power design. most effective technique is adiabatic logic circuit design energy-efficient hardware. This paper presents two approaches for the low circuits, modified positive feedback (modified PFAL) other direct current diode based (DC-DB PFAL). Logic gates are preliminary components any digital By improving performance basic gates, one can improvise whole system performance. In this proposed architecture OR/NOR, AND/NAND, XOR/XNOR presented using said their results analyzed powerdissipation, delay, power-delay-product rise time compared with techniques along conventional complementary metal oxide semiconductor (CMOS) designs reported literature. It been found that DC-DB PFAL outperform percentage improvement 65% NOR gate 7% NAND 34% XNOR over at 10 MHz respectively.